The present invention relates to metal-oxide semiconductor devices and, more particularly, to vertical MOS devices and their fabrication. A major objective of the present invention is the fabrication of vertical CMOS components.
The rapidly expanding microelectronics industry continues to develop new technologies and process refinements, yielding extremely dense circuitry upon single semiconductor chips. The number of components that may be included on a single silicon integrated circuit nearly doubles every year. Advances in microelectronics have had a major impact on the size and cost of computer hardware. The increasing capacity of semiconductor memory devices has provided cheap, efficient means of accessing and storing large amounts of information. Further, the means to integrate a central processing unit on a single chip has allowed the incorporation of powerful computing systems in automobiles, appliances, and in home and office computers.
Several technologies exist for producing microelectronic circuits in semiconductor materials. Scientists first explored bipolar technology, using the operational principles of the original transistor, to create small-and medium-scale integrated circuit devices, each having upwards of 200 separate logical gates on a single silicon substrate. Metal Oxide Semiconductor technology (or MOS), while conceptually simpler than bipolar technology, did not emerge until later, because of material problems associated with making high-quality gate oxides.
The MOS fabrication procedure starts with a thin silicon wafer, from which each IC chip will be cut. The wafer is cut from a pure silicon crystal doped with impurities to be either a p-type or n-type material. P-type semiconductors possess an excess number of "holes", or positively-charged carriers. N-type semiconductors possess an excess number of electrons, or negatively-charged carriers.
Typically, the MOS transistor is laid out across the surface of the silicon wafer, which for this example will be of p-type silicon. Two n-type regions are formed in an upper silicon layer by diffusing impurities at specific areas on the silicon surface. These regions are usually referred to as the "source" and "drain" terminals of the device and are separated by a "channel" region, composed of the original p-type silicon material. A third terminal of the device, termed the "gate", comprises a layer of polycrystalline silicon (polysilicon) deposited on top of a thin (typically 100-200 .ANG. thick) insulating layer of silicon dioxide. The gate is positioned directly over the channel region of the MOS transistor, and is normally heavily diffused with impurities so that it behaves as a good conductor.
The gate acts as one plate of a capacitor, while the relatively low-conductivity silicon channel acts as the other plate. A sufficiently positive potential applied to the gate electrode induces a negative charge in the silicon semiconductor and acts to repel the majority carrier (the holes) from the channel region's surface. As the potential applied to the gate increases, so too does the concentration of minority carrier electrons at the interface between the oxide and the silicon substrate and eventually this minority concentration becomes comparable with the density of majority carrier holes to produce what is termed an inversion layer. Since the inversion charge at the oxide-semiconductor interface provides a conductive channel between the source and drain, a potential difference applied between these two electrodes causes a current to flow between them. The device is then said to be in the ON state and the gate voltage required to allow conduction to occur is known as the threshold voltage. Prior to inversion, the channel is not formed, hence no current can flow, and the device is said to be OFF. The gate of a MOS transistor therefore acts as a switch, between the source and drain, which is open or closed depending on the voltage applied to the gate.
The MOS transistor is the central element in many integrated circuit applications, allowing electronics designers to cascade logical on/off devices by replicating and connecting together an array of MOS transistors across a silicon chip. An extremely important factor in the advancement of integrated circuit technology has been the scaling down of device dimensions. Until recently, the manufacturing penalty which has been required to achieve scaling reductions has been low and has been considerably outweighed by the resulting improvements in circuit performance. Stated algebraically, if all dimensions of a device are scaled by a given factor k, the scaling provides a k.sup.2 increase in devices on a given sized chip. The commonly-used constant field approach to scaling assumes that as the dimension scales so do all voltages (both supply and threshold voltages) within the circuit by the same ratio, so that the current in the chip will also be reduced by k and the power dissipated in each device by k.sup.2. Therefore the overall power consumption of a chip of given size remains unaltered. A further benefit of scaling is that individual gates operate k times faster. Therefore, the functional throughput of the chip (defined as the number of gates multiplied by the clock rate of the device divided by its power consumption) should scale as k.sup.3. Since functional throughput increases so dramatically while holding power requirements constant, there are enormous benefits gained from scaling MOS integrated circuits to ever smaller sizes.
Recently, however, production and material limitations have begun to hamper continual reduction of MOS circuit size. Several considerable production limitations involve the ability to fabricate structures reproducibly across a whole wafer as one shrinks each surface feature. Integrated circuits are laid out onto silicon wafers by photolithographic processes, whereby a succession of different photographic plates bearing the locations and sizes of individual features (for example, the source regions across a chip) are optically projected onto a wafer coated with photoresist. The photoresist hardens during subsequent processing in those places where it is exposed. These hardened areas form a mask for subsequent etching or impurity implantation steps. However, as the dimensions of IC devices approach the wavelengths used by the optical projectors, diffraction effects begin to blur fine circuit patterns, degrading manufacturing control. Hence the ability to define and resolve patterns of this size using conventional optical lithographic techniques ultimately becomes diffraction limited, such that continuously shorter wavelengths are needed.
Further, imaging individual patterns is itself not sufficient for the fabrication of a large scale integration (or LSI) chip; patterns must also be aligned (or registered) in the correct place relative to previous ones. For this reason the minimum linewidth that can be used for LSI chips is not the smallest that can be imaged onto a silicon wafer, but the smallest that can be controlled within critical tolerances. Typically, the mask for a single chip begins with a reticle plate containing an enlarged (perhaps by 5 times) image of the patterns appropriate to one layer on one chip. The image is then photoreduced and repeatedly stepped over a two-dimensional array to produce a final mask. A series of these masks are used to lay out each successive process step in the production of the completed integrated circuit. Registration can be improved by using single-chip masks and reduction-projection printers, which step the individual chip pattern over the entire wafer. These projection systems offer advantages (over prior full wafer printers) of higher resolution, better chip-by-chip alignment and less sensitivity to dust on the mask. However, they are more expensive, take longer to expose a wafer, and, ultimately, also suffer from alignment and resolution problems as the complexity in the number of masks (and integrated devices) increases and the size of individual device elements grows smaller. As circuit features shrink in size, the alignment, or registration, of successive patterns becomes increasingly difficult.
Self-alignment in semiconductor processing has been attempted to solve registration problems and limit the number of masks required. In a self-aligning process, certain features or spacers are created in the semiconductor wafer using conventional masks. Spacers may be created by forming a conformal deposit of an oxide or nitride, and then using an anisotropic etch to remove the deposit from horizontal areas but leave thin deposited spacers along vertical walls (for instance, the walls of a patterned photoresist mask). These spacers then function as a secondary mask in further processing steps. By using the spacer portions of the layout to mask other wafer areas, circuit features can be aligned to one another by a natural and accurate process. The number of masks required is also reduced. While widely used in MOS processing, self-alignment techniques are often limited to only suitable device designs, however, they still provide attractive methods for scale reductions.
In addition to problems inherent in the photolithographic methods of producing very large scale integrated (or VLSI) circuits, several fundamental material and device structure problems also limit the scale reductions of current MOS-technology ICs. As the channel length, the distance between the MOS transistor's source and drain regions, decreases, the depletion regions formed at the source-to-substrate and the drain-to-substrate p-n junctions begin to overlap. When this occurs, control of the device by the gate electrode is lost. The width of these depletion regions can be decreased by either reducing the circuit supply voltage or by increasing the substrate doping concentration. However, increasing the doping concentration also increases the electric field required at the gate to turn the MOS transistor on, and this field must be maintained below the breakdown field of the oxide layer separating the gate from the channel region. In addition, parasitic capacitance goes up, slowing circuit operation. Hot electron degradation has been perhaps the major limitation on scale-reductions in VLSI circuits. In order to avoid the onset of avalanche in MOS transistors, the electric field in the channel region must be maintained within certain limits. As channel length shrinks, channel voltage must therefore also decrease, leading to reduced current flow and slower circuit operation. However, in addition to these problems, the threshold operation voltage V.sub.T proves to be a fundamental limit to scaling of MOS transistor devices, preventing further decreases in voltage.
Another major problem in scaling MOS transistors results from the relationship of the channel region's depth to its length. As these two dimensions become comparable, current not only flows directly through the channel from source to drain, but also (at high enough electric fields) through the substrate, having deleterious effects on MOS operation. At small geometries and high terminal biases, some of the parasitic current can flow from the source to the drain, outside of the MOS channel. Under what is termed parasitic bipolar action, the source-to-substrate junction can then become forward biased, causing electrons to be injected into the substrate. Although much of the current will be collected by the drain, some will diffuse several hundred microns away and interfere with the operation of other parts of the circuit. Another deleterious effect of excess injected electrons is that of latch-up. Latch-up occurs where neighboring transistor areas form a parasitic NPNP diode. The NPNP diode can suddenly turn on by virtue of the parasitic current once current flow between the two transistor regions is made to cross a critical threshold, interrupting normal circuit operation, and even permanently damaging the circuitry.
To attempt to eliminate the spurious parasitic currents in MOS microelectronic circuits, attention has been placed on so-called silicon-on-insulator (or SOI) technologies. The motivating idea behind these new approaches is that of eliminating the portion of the silicon substrate which extends below the actual MOS transistor. Current in an SOI transistor would have nowhere else to flow but through the channel region itself. SOI technology isolates one circuit component from another by allowing the construction of each component in its own "island" of silicon. The various SOI techniques promise design and process simplicity, high circuit density and immunity from the effects of parasitic transistor activity. In addition, SOI technology promises to lessen the effects of hot electron degradation when scaling circuit devices to smaller dimensions.
One potential SOI technique employs a substrate of sapphire and is termed silicon-on-sapphire. The process involves depositing an epitaxial layer of silicon onto a single crystal sapphire surface such that single crystal growth of the silicon layer (necessary for transistor fabrication) is promoted. Epitaxial deposition refers to any process for growing single-crystal layers upon another substrate. While some success has been made with this technology, several significant problems exist. Namely, large thermal mismatches may exist between the sapphire substrate and the silicon layer, and the process yields a silicon layer with residual defects and lacking a unique orientation. Moreover, the cost of the sapphire outweights its advantages for most commercial applications.
Other SOI approaches have also been investigated. In one of these approaches, very large doses of oxygen or nitrogen are implanted at high energy to form a buried silicon oxide or nitride layer under the bulk silicon wafer surface. Promising results have been achieved using this approach, but optimization of the ion implantation process must be accomplished to reduce the implantation time and cost to an economic level. In another approach, a polycrystalline silicon layer is deposited onto an oxidized silicon wafer and then melted to recrystallize into a single-crystal device-usable form. A third approach attaches a silicon wafer, before the integrated circuits have been fabricated, to a new substrate and etches away part of the wafer, to insulate each eventual circuit from parasitic effects.
While all of the SOI approaches attempted so far show promise in solving some of the existing material problems such as parasitic current paths, none have as yet provided cost-effective, commercially viable techniques for reproducibly fabricating large scale integrated circuits. Bi-polar activity in SOI transistors can lead to a "kink" effect, whereby excess charge carriers can distort transistor characteristics and require complicated design changes. To eliminate the kink effect, SOI transistors often require an extra terminal to bleed parasitic charge away, which makes for bulkier circuitry. Ultrathin SOI transistors can encourage parasitic bipolar transistor snap-back action that degrades circuit operation; this effect can be reduced by very low voltage CMOS circuit design. None of these SOI techniques directly addresses the fabrication problems related to photolithography and registration of short channel transistors.
Another novel MOS approach creates a Surrounding Gate Transistor (or SGT). An SGT surrounds a vertical cylindrical channel with a gate layer. A drain electrode is placed on the top portion of the vertical channel and a source electrode surrounds the channel's base. By building a MOS device upwards, horizontal chip space may be saved while also limiting parasitic current flow. In addition, SGT technology may provide similar advantages as SOI methods for minimizing hot electron degradation effects. However, the SGT techniques may have difficulty controlling critical channel length dimensions, since these depend on etch-depth tolerances, and the techniques still require all the complex processing steps of conventional CMOS devices.
What is needed is an improved method and system for fabricating MOS integrated circuits which allows for increased miniaturization of individual circuit elements. More specifically, the method should resolve both the process problems of photolithographic circuit resolution and pattern registration and the material problems associated with the close proximity of conventional MOS devices, such as latch-up and parasitic current flows. In addition, the method should provide a simple and cost-effective technology for reliably producing VLSI integrated circuit chips.